Adders-cont.-

The adders discussed in the previous section have been limited to adding single-digit binary numbers and carries. The largest sum that can be obtained using a full adder is 11 2.

Parallel adders let us add multiple-digit numbers. If we place full adders in parallel, we can add two- or four-digit numbers or any other size desired.

The figure below uses STANDARD SYMBOLS to show a parallel adder capable of adding two, two-digit binary numbers. In previous discussions we have depicted circuits with individual logic gates shown. Standard symbols (blocks) allow us to analyze circuits with inputs and outputs only. One standard symbol may actually contain many and various types of gates and circuits. The addend would be input on the A inputs (A 2 = MSD, A 1 = LSD), and the augend input on the B inputs (B 2 = MSD, B 1 = LSD). For this explanation we will assume there is no input to C 0 (carry from a previous circuit).

Parallel binary adder.

Now let�s add some two-digit numbers. To add 10 2 (addend) and 01 2 (augend), assume there are numbers at the appropriate inputs. The addend inputs will be 1 on A 2 and 0 on A 1. The augend inputs will be 0 on B 2 and 1 on B 1. Working from right to left, as we do in normal addition, let�s calculate the outputs of each full added.

With A 1 at 0 and B 1 at 1, the output of adder 1 will be a sum (S 1) of 1 with no carry (C 1). Since A 2 is 1 and B 2 is 0, we have a sum (S 2) of 1 with no carry (C 2) from adder 1. To determine the sum, read the outputs (C 2, S 2, and S 1) from left to right. In this case, C2 = 0, S 2 = 1, and S 1 = 1. The sum, then, of 10 2 and 01 2 is 011 2 or 11 2.

To add 11 2 and 01 2, assume one number is applied to A 1 and A 2, and the other to B 1 and B 2, as shown in the figure below. Adder 1 produces a sum (S 1) of 0 and a carry (C 1) of 1. Adder 2 gives us a sum (S 2) of 0 and a carry (C 2) of 1. By reading the outputs (C 2, S 2, and S 1), we see that the sum of 11 2 and 01 2 is 100 2.

Parallel addition.

First, apply the addend and augend to the A and B inputs. Calculate the output of each full adder beginning with full adder 1. With A 1 and B 1 at 1, S 1 is 0 and C 1 is 1. Since all three inputs (A 2, B 2, and C 1) to full adder 2 are 1, the output will be 1 at S 2 and 1 at C 2. The output of the circuit, as you read left to right, is 110 2, the sum of 11 2 and 11 2.

Parallel adders may be expanded by combining more full adders to accommodate the number of digits in the numbers to be added. There must be one full adder for each digit.

SUBTRACTION

Subtraction is accomplished in computers by the R�s complement and add method. This is the same method you used in chapter 1 to subtract binary numbers.

R�s complement subtraction allows us to use fewer circuits than would be required for separate add and subtract functions. Adding X-OR gates to full adders, as shown in the figure below, enables the circuit to perform R�s complement subtraction as well as addition.

R's complement adder/subtracter.

In the add mode, the outputs of the X-OR gates will be the same as the B inputs. Addition takes place in the same manner as described in parallel addition.

Before we attempt to show subtraction, let�s review R�s complement subtraction. To subtract 102 from 112, write down the minuend (11 2). Perform the R�s complement on the subtrahend. Now add the minuend and the complemented subtrahend.

11 2 minuend

+ 10 2 R�s complement

10 1 Difference

Disregard the most significant 1, and the difference between 112 and 102 is 012. The most significant 1 will not be used in the example shown in the following paragraph.

Now let�s subtract 10 2 from 11 2 using the adder/subtracter circuit. The minuend (11 2) is input on the A terminals, and the subtrahend (10 2) is input on the B terminals. In the subtract mode, a 1 from the control circuit is input to each of the X-OR gates and to the C0 carry input. By applying a 1 to each of the X-OR gates, you find the output will be the complement of the subtrahend input at B 1 and B 2.

Since B 1 is a 0, the output of X-OR 1 will be 1. The input B 2 to X-OR 2 will be inverted to a 0. The HIGH input to C 0 acts as a carry from a previous circuit. The combination of the X-OR gates and the HIGH at C 0 produces the R�s complement of the subtrahend. The full adders add the minuend and the R�s complement of the subtrahend and produce the difference. The output of C 2 is not used. The outputs of S 2 and S 1 are 0 and 1, respectively, indicating a difference of 01 2. Therefore, 11 2 minus 10 2 equals 01 2.

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